Metal cap for contact resistance reduction

ABSTRACT

A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.

TECHNICAL FIELD

Embodiments of the present disclosure generally relate to transistorsand methods for forming transistors. In particular, transistor contacts,for example source/drain contacts, have reduced resistance.

BACKGROUND

Integrated circuits have evolved into complex devices that can includemillions of transistors, capacitors, and resistors on a single chip. Inthe course of integrated circuit evolution, functional density (i.e.,the number of interconnected devices per chip area) has generallyincreased while geometry size (i.e., the smallest component (or line)that can be created using a fabrication process) has decreased.

Microelectronic devices are fabricated on a semiconductor substrate asintegrated circuits in which various conductive layers areinterconnected with one another to permit electronic signals topropagate within the device. An example of such a device is acomplementary metal-oxide-semiconductor (CMOS) field effect transistor(FET) or MOSFET, including both planar and three-dimensional structures.An example of a three-dimensional structure is a FinFET device.

Drive current, and therefore speed, of a transistor is proportional to agate width of the transistor. Faster transistors generally requirelarger gate width. There is a trade-off between transistor size andspeed, and “fin” field-effect transistors (finFETs) have been developedto address the conflicting goals of a transistor having maximum drivecurrent and minimum size. FinFETs are characterized by a fin-shapedchannel region that greatly increases the size of the transistor withoutsignificantly increasing the footprint of the transistor.

An exemplary finFET or MOSFET includes a gate electrode on a gatedielectric layer on a surface of a semiconductor substrate. Source/drainregions are provided along opposite sides of the gate electrode. Thesource and drain regions are generally heavily doped regions of thesemiconductor substrate. Usually a capped silicide layer, for example,titanium silicide capped by titanium nitride, is used to couplecontacts, e.g., active and/or metal contacts, to the source and drainregions. Including a nitrogen-containing capping layer, however, canundesirably contribute to contact resistance.

Further, during middle-of-line (MOL) processes, a minimum via resistancefor the MOL structures are targeted. A liner material (e.g., titaniumnitride) is often required to improve adhesion of metals to dielectricmaterials to pass post-processing steps such as chemical-mechanicalplanarization (CMP) and to enhance CVD nucleation. However, the presenceof the liner adds to the via resistance.

Therefore, there is a need in the art for transistors and MOLapplications with decreased resistance.

SUMMARY

One or more embodiments are directed to a contact stack of asemiconductor device, which comprises: a source/drain region; a metalsilicide layer above the source/drain region; a metal cap layer indirect contact with the metal silicide layer; and a conductor in contactwith the metal cap layer.

Additional embodiments are directed to a semiconductor devicecomprising: a contact stack on the substrate, a dielectric layeradjacent to the contact stack, and a metal gate adjacent to thedielectric layer. The contact stack comprises: a source/drain regioncomprising: silicon, germanium, silicon-germanium, or a group III/Vcompound semiconductor; a metal silicide layer on the source/drainregion, the metal silicide layer comprising: titanium silicide, cobaltsilicide, ruthenium silicide, nickel silicide, molybdenum silicide, oralloys thereof; a metal cap layer directly on the metal silicide layer,the metal cap layer comprising: tungsten, ruthenium, molybdenum, oralloys thereof; and a conductor on the metal cap layer.

Further embodiments are directed to a method comprising: depositing ametal silicide layer in a feature of a substrate in a first processingchamber, the feature comprising a bottom wall and sidewalls; moving thesubstrate to a second processing chamber that is integrated with thefirst processing chamber such that there is not an air break between thefirst and second processing chambers; preparing a metal cap layerdirectly on the metal silicide layer; and depositing a conductor on themetal cap layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

FIG. 1 is a cross-sectional view of a contact stack in accordance withone or more embodiments;

FIG. 2 is a cross-sectional view of a semiconductor device in accordancewith one or more embodiments;

FIG. 3A is a flowchart of a method for forming a contact stack accordingto FIG. 1 in accordance with one or more embodiments;

FIG. 3B is a flowchart of a method for forming a contact stack accordingto one or more embodiments;

FIGS. 4A-4H illustrate various views of a stack during different stagesof the method of FIG. 3B; and

FIG. 5 is a cluster tool accordance with one or more embodiments.

DETAILED DESCRIPTION

Before describing several exemplary embodiments of the disclosure, it isto be understood that the disclosure is not limited to the details ofconstruction or process steps set forth in the following description.The disclosure is capable of other embodiments and of being practiced orbeing carried out in various ways.

As used in this specification and the appended claims, the term“substrate” refers to a surface, or portion of a surface, upon which aprocess acts. It will also be understood by those skilled in the artthat reference to a substrate can also refer to only a portion of thesubstrate, unless the context clearly indicates otherwise. Additionally,reference to depositing on a substrate can mean both a bare substrateand a substrate with one or more films or features deposited or formedthereon.

A “substrate” as used herein, refers to any substrate or materialsurface formed on a substrate upon which film processing is performedduring a fabrication process. For example, a substrate surface on whichprocessing can be performed include materials such as silicon, siliconoxide, strained silicon, silicon on insulator (SOI), carbon dopedsilicon oxides, amorphous silicon, doped silicon, germanium, galliumarsenide, glass, sapphire, and any other materials such as metals, metalnitrides, metal alloys, and other conductive materials, depending on theapplication. Substrates include, without limitation, semiconductorwafers. Substrates may be exposed to a pretreatment process to polish,etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/orbake the substrate surface. In addition to film processing directly onthe surface of the substrate itself, in the present disclosure, any ofthe film processing steps disclosed may also be performed on anunderlayer formed on the substrate as disclosed in more detail below,and the term “substrate surface” is intended to include such underlayeras the context indicates. Thus for example, where a film/layer orpartial film/layer has been deposited onto a substrate surface, theexposed surface of the newly deposited film/layer becomes the substratesurface.

As used herein, the term “fin field-effect transistor (FinFET)” refersto a MOSFET transistor built on a substrate where the gate is placed ontwo or three sides of the channel, forming a double- or triple-gatestructure. FinFET devices have been given the generic name FinFETsbecause the channel region forms a “fin” on the substrate. FinFETdevices have fast switching times and high current density.

As used herein, “consists essentially of” with respect to composition ofa layer means that the stated elements compose greater than 95%, greaterthan 98%, greater than 99% or greater than 99.5% of the stated materialon an atomic basis. For the avoidance of doubt, no stoichiometric ratiosare implied by the identification of materials disclosed herein. Forexample, a TiSi material contains titanium and silicon. These elementsmay or may not be present at a 1:1 ratio.

Embodiments herein relate to contact stacks, semiconductor devices, andmethods of making the same, which advantageously offer reducedresistance in transistor contacts. Resistance is reduced by eliminatingnitrogen-based layers, e.g., a nitride cap layer and/or a nitride linerlayer. Use of a metal-based cap layer on top of a silicide layer atcontact areas, e.g., source and drain, eliminates the use of anitrogen-based barrier film between silicide and conductor, e.g., plugmetal. Contact resistance is advantageously reduced by direct contactbetween the silicide and plug metal, e.g., direct contact of silicidewith different low resistivity metals (W, Ru, Mo, . . . ). Themetal-based cap layer advantageously inhibits silicide from alterationby process chemicals (O₂, F, Cl₂, and the like).

Contact resistance (Ω) provides a measure of the opposition to electriccurrent flow due to contacting interfaces. In a contact stack, anitride-based cap according to prior art contributed upwards of 25% ofthe stack's contact resistance. Experiments of embodiments herein wherea nitride-based cap (TiN) was replaced with a metal cap (W) resulted ina reduction in contact resistance on the order of 20%.

Metal cap layers herein are effective to inhibit and/or eliminatediffusion of undesirable elements into and/or silicon out of theunderlying metal silicide layer. For example, a tungsten metal caplayer, e.g., having a thickness of about 20 to 30 Angstroms, iseffective to inhibit and/or eliminate diffusion of one or more of:oxygen, argon, fluorine, silicon.

Processes according to one or more embodiments eliminate an air break,which facilitates the removal of a nitrogen-based cap layer. Depositionof a metal cap layer is done using low energy physical vapor deposition(PVD) technology, which replaces the use of chemical vapor deposition(CVD) and eliminates the need for a nitrogen-based liner for CVDnucleation. Low energy PVD technology also advantageously reducespotential for damage to the metal silicide layer.

According to one or more embodiments, devices and methods of formationthese devices are particularly useful in forming FinFET devices and willbe described in that context. Other devices and applications are alsowithin the scope of the invention.

FIG. 1 illustrates a cross-sectional view of an exemplary contact stack101 suitable for a semiconductor device. Stack 101 comprises asource/drain region 110. In some embodiments, the source/drain region110 comprises silicon, germanium, silicon-germanium, or a group III/Vcompound semiconductor. Above the source/drain region 110 is a metalsilicide layer 120. In some embodiments, the metal silicide layer 120comprises: titanium silicide, cobalt silicide, or ruthenium silicide. Indirect contact with the metal silicide layer 120 is a metal cap layer130. In one or more embodiments, the contact stack 101 excludes a metalnitride layer in direct contact with the metal silicide layer. In one ormore embodiments, the entire contact stack 101 excludes a metal nitridelayer. In some embodiments, the metal cap comprises: tungsten,ruthenium, molybdenum, or alloys thereof. Above the metal cap layer is aconductor 140. In one or more embodiments, the metal cap layer is incontact with conductor 140. The conductor 140 may comprise a combinationof layers to provide an active contact and/or a metal contact. In one ormore embodiments, the conductor 140 comprises a metal selected from thegroup consisting of: tungsten, ruthenium, and cobalt.

In some embodiments, the metal silicide layer 120 comprises or consistsessentially of TiSi. In some embodiments, the metal cap layer 130comprises or consists essentially of tungsten (W).

FIG. 2 illustrates a cross-sectional view of a semiconductor device 200comprising: a substrate 205, a contact stack 201 on the substrate 205, adielectric layer 250, and a metal gate 260. The contact stack 201comprises: a source/drain region 210, a metal silicide layer 220 on thesource/drain region 210, a metal cap layer 230 in direct contact withthe metal silicide layer 220, and a conductor 240 above the metal caplayer 230. In one or more embodiments, the conductor 240 is in contactwith the metal cap layer 230. In one or more embodiments, the conductor240 is in direct contact with the metal cap layer 230.

As shown in FIG. 2, in one or more embodiments, the source/drain region210 is formed on the substrate 205. In other embodiments, a source/drainregion may be integral to and/or extend from a body of the substrate.

In some embodiments, the source/drain region 210 comprises silicon,germanium, silicon-germanium, or a group III/V compound semiconductor.In some embodiments, the metal silicide layer 220 comprises: titaniumsilicide, cobalt silicide, ruthenium silicide, nickel silicide,molybdenum silicide, or alloys thereof. In one or more embodiments, thecontact stack 201 excludes a metal nitride layer on the metal silicidelayer. In one or more embodiments, the entire contact stack 201 excludesa metal nitride layer. In some embodiments, the metal cap layer 230comprises: tungsten, ruthenium, molybdenum, or alloys thereof. Theconductor 240 may comprise a combination of layers to provide an activecontact and/or a metal contact. In one or more embodiments, theconductor 240 comprises a metal selected from the group consisting of:tungsten, ruthenium, and cobalt.

The dielectric layer 250 insulates the contact stack 201 from the metalgate 260. In one or more embodiments, the dielectric layer directlycontacts the contact stack. In one or more embodiments, thesemiconductor device 200 excludes a metal nitride layer between thecontact stack 201 and the dielectric layer 250. In one or moreembodiments, the entire semiconductor device 200 excludes a metalnitride layer. In one or more embodiments, the dielectric layer 250comprises a dielectric material, such as an oxide or a nitride, forexample: SiOx (e.g., SiO₂), SiN, SiCN, or other suitable dielectricmaterial.

In some embodiments, the metal silicide layer 220 comprises or consistsessentially of TiSi. In some embodiments, the metal cap layer 230comprises or consists essentially of tungsten (W).

In some embodiments, the metal silicide layer has a thickness of greaterthan or equal to 20 Å to less than or equal to 60 Å, and all values andsubranges therebetween. In some embodiments, the metal silicide layerhas a thickness of about 40 Å, which includes 40 Å±10%. In one or moreembodiments, the metal silicide layer is a selectively deposited layer.In one or more embodiments, the metal silicide layer is a selectivelayer of TiSi.

In some embodiments, the metal cap layer has a thickness of greater thanor equal to 10 Å to less than or equal to 50 Å, and all values andsubranges therebetween. In some embodiments, the metal cap layer has athickness of about 30 Å, which includes 30 Å±10%. In one or moreembodiments, the metal cap layer is deposited by a PVD process.

Referring to FIG. 3A, a general embodiment relates to a method 300 ofmanufacturing a contact stack of a semiconductor device. The method 300starts at operation 310 by depositing a metal silicide layer in afeature of a substrate. At operation 320, a metal cap layer is prepareddirectly on the metal silicide layer in the absence of an air break. Forexample, operation 310 is conducted in a first chamber that isintegrated with a second chamber where operation 320 is conducted. Atoperation 330, a conductor is deposited on the metal cap layer. In oneor more embodiments, operation 330 is conducted in a third chamber. Inone or more embodiments, the method comprises: depositing a metalsilicide layer in the feature of a substrate in a first processingchamber; moving the substrate to a second processing chamber that isintegrated with the first processing chamber such that there is not anair break between the first and second processing chambers; preparing ametal cap layer directly on the metal silicide layer; and depositing aconductor on the metal cap layer.

Referring to FIGS. 3B to 4A-4H, another embodiment relates to a method350 of manufacturing a contact stack of a semiconductor device 400. Themethod 350 starts at operation 360 by depositing a metal silicide layer420 in a feature 402 of a substrate 405 as shown in FIG. 4A. In one ormore embodiments, the feature 402 comprises a source/drain region 410 asa bottom wall 402 b, and sidewalls 402 s comprising a dielectricmaterial 450.

The feature 402 may be formed by methods known in the art. As anexample, the feature 402 may be a trench prepared by etching adielectric layer to reach a source/drain region and there after by apre-cleaning process (e.g., wet etch and/or dry etch) to removecontaminants. The wet etch process may utilize ammonia or hydrogenfluoride solution. The dry etch process may be a plasma etch process andmay utilize a fluorine or hydrogen containing etchant. The pre-cleanprocess would not substantially remove any portion of the source/drainregion.

Reference to “ source/drain region” is a source region or a drain regionor a merged source and drain region. In one or more embodiments, thesource/drain region 410 is fabricated from a semiconductor material thatis grown epitaxially on one or more surfaces of the substrate 405.

In one or more embodiments, the metal silicide layer 420 is depositedselectively onto the bottom wall 402 b. In one or more embodiments, themetal silicide layer 420 is deposited by a selective epitaxialdeposition process such that the metal silicide layer 420 is formed onthe bottom 402 b of the feature 402, and not on sidewalls 402 s of thefeature 402 as a result of the selective epitaxial deposition process.

In general, any suitable precursors can be used for the metal silicidelayer. For a titanium silicide layer, titanium precursors can include,but are not limited to TiCl₄, TiBr₄, Til₄, TiF₄, tetrakisdimethylaminotitanium; silicon-based precursors can include but are not limited tosilanes (e.g., silane(Si₁H₄), disilane (Si₂H₆), trisilane (Si₃H₈),tetrasilane (Si₄H₁₀), isotetrasilane, neopentasilane (Si₆H₁₂),cyclopentasilane (Si₆H₁₀), hexasilane (C₆H₁₄), cyclohexasilane (Si₆H₁₂)or, in general, Si_(z)H_(a) where z=1 or more, and combinationsthereof), organosilanes, and/or halosilanes (of Si_(g)H_(h)X_(i), whereeach X is a halogen independently selected from F, Cl, Br and I, g isany integer greater than or equal to 1, h and i are each less than orequal to 2 g+2 and h+i is equal to 2 g+2) as a co-reactant.

The order in which the substrate is exposed to the precursors can bevaried. The exposures may repeat in a deposition cycle. Further,exposure to a precursor may be repeated within a single depositioncycle.

At operation 370, a metal cap material 432 is deposited directly on themetal silicide layer 420, as shown in FIG. 4B, in the absence of an airbreak. In one or more embodiments, operations 360 and 370 are conductedin different processing chambers that are integrated. As such, transferbetween the chambers is performed without breaking vacuum and/or withoutexposure to ambient air.

An exemplary process for depositing the metal cap material directly onthe metal silicide layer is by a physical vapor deposition (PVD)process. In one or more embodiments, depositing the metal cap materialdirectly on the metal silicide layer is conducted in (PVD) processchamber. In one or more embodiments, the conditions of the PVD processchamber are low energy. In one or more embodiments, the PVD processchamber is a RF-PVD process chamber. In one or more embodiments,temperature of the PVD chamber within a range of room temperature (e.g.,25° C.) to 600° C., including all values and subranges therebetween. Inone or more embodiments, bias is in a range of 0 W to 400 W, includingall values and subranges therebetween. In one or more embodiments,direct current is in a range of 0 W to 500 W. In one or moreembodiments, radio frequency is in range of 1 kHz to 10 kHz.

In an embodiment, the PVD chamber has conditions of: a chambertemperature of 350° C. to 450° C.; a chamber pressure of 120 mT±50 mT; abias in a range of 0 W to 200 W; a direct current (DC) in a range of 0 Wto 500 W; and a radio frequency (RF) in a range of 1 kHz to 10 kHz. Inone or more embodiments, the PVD chamber has conditions of: a chambertemperature of 400° C.±50° C.; a chamber pressure of 120 mT ±50 mT; abias in a range of 0 W to 200 W; a direct current (DC) of 500 W±50 W;and a radio frequency (RF) of 3 kHz±1 kHz. In one or more embodiments,the PVD process is a plasma-enhanced PVD. In one or more embodiments,the plasma-enhanced PVD includes a pulsed radio frequency (RF) plasma.

According to one or more embodiments, deposition of the metal capmaterial 432 is by bottom fill as shown in FIG. 4B, which requiresfurther processing to prepare a metal cap layer 430 at operation 380prior to deposition of a conductor at operation 390.

In general, any suitable metal cap precursor can be used for the metalcap material and/or metal cap layer.

Operation 380 to prepare a metal cap layer includes FIGS. 4C-4G. In FIG.4C, according to one or more embodiments, a material 434, which may be aspin-on or gap-fill material, is deposited over the entirety of thedevice 400. In one or more embodiments, the material 434 is a spin-onmaterial, which is a carbon-based material. In one or more embodiments,the material 434 is a CVD gap-fill material, which is a dielecticmaterial.

FIG. 4D, according to one or more embodiments, depicts etching of atleast a portion of the material 434. For spin-on material, etching maybe conducted by a dry etch process, which may utilize a plasma etchprocess and may utilize a hydrogen or nitrogen or oxygen containingetchant. For tungsten material, etching may be conducted by a dry etchprocess, which may utilze oxidizing exposed tungsten followed by WF₆.Alternatively, according to one or more embodiments, after depositingthe material 434 shown in FIG. 4C, a chemical mechanical polishing (CMP)of at least a portion of the material and the metal cap layer above thedielectric material may be applied followed by an etching of at least aportion of the material 434 in the trench.

In FIG. 4E, the metal cap material 432 is etched to remove the metal capmaterial 432 from a portion of the sidewalls 402 s above the material434 and the top surfaces of the dielectric material 450.

In FIG. 4F, the remaining material 434 is etched away, leaving the metalcap material 432 exposed.

In FIG. 4G, the exposed metal cap material 432 is etched (e.g., wet etchand/or dry etch) to form a metal cap layer 430. An etching with oxygen-,fluorine-, or chlorine-based gas may be conducted, for example.

After formation of the metal cap layer 430, at operation 390 and shownin FIG. 4H, a conductor 440 is deposited on the metal cap layer 430. Theconductor 440 is fabricated from an electrically conductive material,such as a metal. In one or more embodiments, the conductor comprises ametal selected from the group consisting of: tungsten, ruthenium, andcobalt. Optionally, prior to deposition of the conductor 440 there is apre-clean operation conducted. In one or more embodiments, the pre-cleanoperation prior to deposition of the conductor comprises a plasmatreatment, e.g., hydrogen plasma.

In one or more embodiments, the conductor is deposited by a selectivedeposition method. In one or more embodiments, the conductor isdeposited by a CVD process and/or a PVD process.

In general, any suitable precursor can be used for the conductor. Forexample, precursors of a tungsten conductor can include, but are notlimited to WCl₆, WBr₆, Wl₆, WF₆.

Consistent with the foregoing, methods of this disclosure can beperformed in the same chamber or in one or more separate processingchambers. In some embodiments, the substrate is moved from the firstchamber to a separate, second chamber for further processing. Thesubstrate can be moved directly from the first chamber to the separateprocessing chamber, or it can be moved from the first chamber to one ormore transfer chambers, and then moved to the separate processingchamber. Accordingly, a suitable processing apparatus may comprisemultiple chambers in communication with a transfer station. An apparatusof this sort may be referred to as a “cluster tool” or “clusteredsystem,” and the like.

Generally, a cluster tool is a modular system comprising multiplechambers which perform various functions including substratecenter-finding and orientation, annealing, deposition and/or etching.According to one or more embodiments, a cluster tool includes at least afirst chamber and a central transfer chamber. The central transferchamber may house a robot that can shuttle substrates between and amongprocessing chambers and load lock chambers. The transfer chamber istypically maintained at a vacuum condition and provides an intermediatestage for shuttling substrates from one chamber to another and/or to aload lock chamber positioned at a front end of the cluster tool. Twowell-known cluster tools which may be adapted for the present disclosureare the Centura® and the Endura®, both available from Applied Materials,Inc., of Santa Clara, Calif. However, the exact arrangement andcombination of chambers may be altered for purposes of performingspecific steps of a process as described herein. Other processingchambers which may be used include, but are not limited to, cyclicallayer deposition (CLD), atomic layer deposition (ALD), chemical vapordeposition (CVD), physical vapor deposition (PVD), etch, pre-clean,chemical clean, thermal treatment such as RTP, plasma nitridation,anneal, orientation, hydroxylation and other substrate processes. Bycarrying out processes in a chamber on a cluster tool, surfacecontamination of the substrate with atmospheric impurities can beavoided without oxidation prior to depositing a subsequent film.

In some embodiments, the first processing chamber and the secondprocessing chamber are part of the same, clustered, processing tool.Accordingly, in some embodiments, the method is an in-situ integratedmethod.

In some embodiments, the first processing chamber and the secondprocessing chamber are different processing tools. Accordingly, in someembodiments, the method is an ex-situ integrated method.

According to one or more embodiments, the substrate is continuouslyunder vacuum or “load lock” conditions, and is not exposed to ambientair when being moved from one chamber to the next. The transfer chambersare thus under vacuum and are “pumped down” under vacuum pressure. Inertgases may be present in the processing chambers or the transferchambers. In some embodiments, an inert gas is used as a purge gas toremove some or all of the reactants. According to one or moreembodiments, a purge gas is injected at the exit of the depositionchamber to prevent reactants from moving from the deposition chamber tothe transfer chamber and/or additional processing chamber. Thus, theflow of inert gas forms a curtain at the exit of the chamber.

The substrate can be processed in single substrate deposition chambers,where a single substrate is loaded, processed and unloaded beforeanother substrate is processed. The substrate can also be processed in acontinuous manner, similar to a conveyer system, in which multiplesubstrate are individually loaded into a first part of the chamber, movethrough the chamber and are unloaded from a second part of the chamber.The shape of the chamber and associated conveyer system can form astraight path or curved path. Additionally, the processing chamber maybe a carousel in which multiple substrates are moved about a centralaxis and are exposed to deposition, etch, annealing, and/or cleaningprocesses throughout the carousel path.

The substrate can also be stationary or rotated during processing. Arotating substrate can be rotated continuously or in discreet steps. Forexample, a substrate may be rotated throughout the entire process, orthe substrate can be rotated by a small amount between exposures todifferent reactive or purge gases. Rotating the substrate duringprocessing (either continuously or in steps) may help produce a moreuniform deposition or etch by minimizing the effect of, for example,local variability in gas flow geometries.

With reference to FIG. 5, additional embodiments of the disclosure aredirected to a processing system 900 for executing the methods describedherein. FIG. 5 illustrates a system 900 that can be used to process asubstrate according to one or more embodiment of the disclosure. Thesystem 900 can be referred to as a cluster tool. The system 900 includesa central transfer station 910 with a robot 912 therein. The robot 912is illustrated as a single blade robot; however, those skilled in theart will recognize that other robot 912 configurations are within thescope of the disclosure. The robot 912 is configured to move one or moresubstrate between chambers connected to the central transfer station910.

At least one pre-clean/buffer chamber 920 is connected to the centraltransfer station 910. The pre-clean/buffer chamber 920 can include oneor more of a heater, a radical source or plasma source. Thepre-clean/buffer chamber 920 can be used as a holding area for anindividual semiconductor substrate or for a cassette of wafers forprocessing. The pre-clean/buffer chamber 920 can perform pre-cleaningprocesses or can pre-heat the substrate for processing or can simply bea staging area for the process sequence. In some embodiments, there aretwo pre-clean/buffer chambers 920 connected to the central transferstation 910.

In the embodiment shown in FIG. 5, the pre-clean chambers 920 can act aspass through chambers between the factory interface 905 and the centraltransfer station 910. The factory interface 905 can include one or morerobot 906 to move substrate from a cassette to the pre-clean/bufferchamber 920. The robot 912 can then move the substrate from thepre-clean/buffer chamber 920 to other chambers within the system 900.

A first processing chamber 930 can be connected to the central transferstation 910. The first processing chamber 930 can be configured as anepitaxy chamber for (selectively) depositing a metal silicide layer andmay be in fluid communication with one or more reactive gas sources toprovide one or more flows of reactive gases to the first processingchamber 930. The substrate can be moved to and from the processingchamber 930 by the robot 912 passing through isolation valve 914.

Processing chamber 940 can also be connected to the central transferstation 910. In some embodiments, processing chamber 940 comprisesphysical vapor deposition (PVD) chamber for depositing a metal capmaterial and/or layer and is fluid communication with one or morereactive gas sources to provide flows of reactive gas to the processingchamber 940. In some embodiments, processing chamber 940 is an RF-PVDchamber. The substrate can be moved to and from the processing chamber940 by robot 912 passing through isolation valve 914.

In some embodiments, processing chamber 960 is connected to the centraltransfer station 910 and is configured to act as a conductor depositionchamber. The processing chamber 960 can be configured to perform one ormore different selective deposition (e.g., CVD or PVD) processes.

In some embodiments, each of the processing chambers 930, 940, and 960are configured to perform different portions of the processing method.For example, processing chamber 930 may be configured to perform themetal silicide layer deposition process, processing chamber 940 may beconfigured to perform the metal cap material and/or layer depositionprocess, and processing chamber 960 may be configured to perform aconductor deposition process. The skilled artisan will recognize thatthe number and arrangement of individual processing chamber on the toolcan be varied and that the embodiment illustrated in FIG. 5 is merelyrepresentative of one possible configuration.

In some embodiments, the processing system 900 includes one or moremetrology stations. For example metrology stations can be located withinpre-clean/buffer chamber 920, within the central transfer station 910 orwithin any of the individual processing chambers. The metrology stationcan be any position within the system 900 that allows the distance ofthe recess to be measured without exposing the substrate to an oxidizingenvironment.

At least one controller 950 is coupled to one or more of the centraltransfer station 910, the pre-clean/buffer chamber 920, processingchambers 930, 940, or 960. In some embodiments, there are more than onecontroller 950 connected to the individual chambers or stations and aprimary control processor is coupled to each of the separate processorsto control the system 900. The controller 950 may be one of any form ofgeneral-purpose computer processor, microcontroller, microprocessor,etc., that can be used in an industrial setting for controlling variouschambers and sub-processors.

The at least one controller 950 can have a processor 952, a memory 954coupled to the processor 952, input/output devices 956 coupled to theprocessor 952, and support circuits 958 to communication between thedifferent electronic components. The memory 954 can include one or moreof transitory memory (e.g., random access memory) and non-transitorymemory (e.g., storage).

The memory 954, or computer-readable medium, of the processor may be oneor more of readily available memory such as random access memory (RAM),read-only memory (ROM), floppy disk, hard disk, or any other form ofdigital storage, local or remote. The memory 954 can retain aninstruction set that is operable by the processor 952 to controlparameters and components of the system 900. The support circuits 958are coupled to the processor 952 for supporting the processor in aconventional manner. Circuits may include, for example, cache, powersupplies, clock circuits, input/output circuitry, subsystems, and thelike.

Processes may generally be stored in the memory as a software routinethat, when executed by the processor, causes the process chamber toperform processes of the present disclosure. The software routine mayalso be stored and/or executed by a second processor (not shown) that isremotely located from the hardware being controlled by the processor.Some or all of the method of the present disclosure may also beperformed in hardware. As such, the process may be implemented insoftware and executed using a computer system, in hardware as, e.g., anapplication specific integrated circuit or other type of hardwareimplementation, or as a combination of software and hardware. Thesoftware routine, when executed by the processor, transforms the generalpurpose computer into a specific purpose computer (controller) thatcontrols the chamber operation such that the processes are performed.

In some embodiments, the controller 950 has one or more configurationsto execute individual processes or sub-processes to perform the method.The controller 950 can be connected to and configured to operateintermediate components to perform the functions of the methods. Forexample, the controller 950 can be connected to and configured tocontrol one or more of gas valves, actuators, motors, slit valves,vacuum control, etc.

The controller 950 of some embodiments has one or more configurationsselected from: a configuration to move a substrate on the robot betweenthe plurality of processing chambers and metrology station; aconfiguration to load and/or unload substrates from the system; aconfiguration to deposit a metal silicide layer, which in one or moreembodiments comprises TiSi; a configuration to deposit a metal caplayer, which in one or more embodiments comprises W, directly on themetal silicide layer; and/or a configuration to deposit a conductor,which in one or more embodiments comprises W.

Reference throughout this specification to “one embodiment,” “certainembodiments,” “one or more embodiments” or “an embodiment” means that aparticular feature, structure, material, or characteristic described inconnection with the embodiment is included in at least one embodiment ofthe disclosure. Thus, the appearances of the phrases such as “in one ormore embodiments,” “in certain embodiments,” “in one embodiment” or “inan embodiment” in various places throughout this specification are notnecessarily referring to the same embodiment of the disclosure.Furthermore, the particular features, structures, materials, orcharacteristics may be combined in any suitable manner in one or moreembodiments.

Although the disclosure herein has been described with reference toparticular embodiments, those skilled in the art will understand thatthe embodiments described are merely illustrative of the principles andapplications of the present disclosure. It will be apparent to thoseskilled in the art that various modifications and variations can be madeto the method and apparatus of the present disclosure without departingfrom the spirit and scope of the disclosure. Thus, the presentdisclosure can include modifications and variations that are within thescope of the appended claims and their equivalents.

What is claimed is:
 1. A contact stack of a semiconductor devicecomprising: a source/drain region; a metal silicide layer above thesource/drain region; a metal cap layer in direct contact with the metalsilicide layer; and a conductor in contact with the metal cap layer. 2.The contact stack of claim 1, wherein the source/drain region comprises:silicon, germanium, silicon-germanium, or a group III/V compoundsemiconductor.
 3. The contact stack of claim 1, wherein the metalsilicide layer comprises: titanium silicide, cobalt silicide, rutheniumsilicide, nickel silicide, molybdenum silicide, or alloys thereof. 4.The contact stack of claim 1, wherein the metal cap layer comprises:tungsten, ruthenium, molybdenum, or alloys thereof.
 5. The contact stackof claim 1, wherein the conductor comprises a metal selected from thegroup consisting of: tungsten, ruthenium, and cobalt.
 6. The contactstack of claim 1 excluding a metal nitride layer in direct contact withthe metal silicide layer.
 7. A semiconductor device comprising: acontact stack on the substrate, the contact stack comprising: asource/drain region comprising: silicon, germanium, silicon-germanium,or a group III/V compound semiconductor; a metal silicide layer on thesource/drain region, the metal silicide layer comprising: titaniumsilicide, cobalt silicide, ruthenium silicide, nickel silicide,molybdenum silicide, or alloys thereof; a metal cap layer directly onthe metal silicide layer, the metal cap layer comprising: tungsten,ruthenium, molybdenum, or alloys thereof; and a conductor on the metalcap layer; and a dielectric layer adjacent to the contact stack, and ametal gate adjacent to the dielectric layer.
 8. The semiconductor deviceof claim 7, wherein the dielectric layer in direct contact with thecontact stack.
 9. The semiconductor device of claim 7 excluding a metalnitride layer in direct contact with the metal silicide layer.
 10. Amethod comprising: depositing a metal silicide layer in a feature of asubstrate in a first processing chamber, the feature comprising a bottomwall and sidewalls; moving the substrate to a second processing chamberthat is integrated with the first processing chamber such that there isnot an air break between the first and second processing chambers;preparing a metal cap layer directly on the metal silicide layer; anddepositing a conductor on the metal cap layer.
 11. The method claim 10,wherein the feature comprises a source/drain region as the bottom wall,and a dielectric material as the sidewalls.
 12. The method claim 10,wherein the metal silicide layer is deposited selectively on the bottomwall.
 13. The method claim 10, wherein the conductor is depositedselectively on the metal cap layer.
 14. The method of claim 10, whereinthe preparing of the metal cap layer directly on the metal silicidelayer is by a physical vapor deposition (PVD) process of a metal capmaterial.
 15. The method of claim 14, wherein the PVD process isconducted under conditions of: a chamber temperature of 350° C. to 450°C.; a chamber pressure of 120 mT ±50 mT; a bias in a range of 0 W to 200W; a direct current (DC) of 0 W to 500 W; and a radio frequency (RF) ina range of 1 kHz to 10 kHz.
 16. The method of claim 14, wherein thepreparing of the metal cap layer comprises depositing of the metal capmaterial, depositing a spin-on or gap-fill material, and thereafteretching of at least a portion of the spin-on or gap-fill material andthe metal cap material.
 17. The method of claim 16 comprising furtheretching of the metal cap material.
 18. The method of claim 14, whereinthe preparing of the metal cap layer comprises depositing of the metalcap material, depositing a spin-on or gap-fill material, and thereafterchemical mechanical polishing (CMP) of at least a portion of the spin-onor gap-fill material and the metal cap material.
 19. The method of claim18 comprising further etching of the metal cap material.
 20. The methodof claim 10, wherein the metal silicide layer comprises: titaniumsilicide, cobalt silicide, ruthenium silicide, nickel silicide,molybdenum silicide, or alloys thereof; and/or the metal cap layercomprises: tungsten, ruthenium, molybdenum, or alloys thereof, and/orthe conductor comprises a metal selected from the group consisting of:tungsten, ruthenium, and cobalt.